`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2022/10/08 20:43:17
// Design Name: 
// Module Name: ImmExt
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
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// Dependencies: 
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module ImmExt(
    input [1:0] ExtOp,
    input [15:0] Imm,
    output reg [31:0] ExtImm
    );
    always @(*) begin
        case (ExtOp)
            2'b00: ExtImm = {{16{Imm[15]}}, Imm};//signed
            2'b01: ExtImm = {16'b0, Imm};//unsigned
            2'b10: ExtImm = {27'b0, Imm[10:6]};//R-Shamt
            2'b11: ExtImm = {Imm, 16'b0};//lui
        endcase
    end
endmodule
